Features
•
Compatible with MCS®-51 Products
• 8K Bytes
of In-System Programmable (ISP) Flash Memory – Endurance: 10,000 Write/Erase
Cycles
• 4.0V to
5.5V Operating Range
• Fully
Static Operation: 0 Hz to 33 MHz
•
Three-level Program Memory Lock
• 256 x
8-bit Internal RAM
• 32
Programmable I/O Lines
• Three
16-bit Timer/Counters
• Eight
Interrupt Sources
• Full
Duplex UART Serial Channel
•
Low-power Idle and Power-down Modes
•
Interrupt Recovery from Power-down Mode
• Watchdog
Timer
• Dual
Data Pointer
• Power-off Flag
• Fast
Programming Time
• Flexible
ISP Programming (Byte and Page Mode)
• Green
(Pb/Halide-free) Packaging Option
Description
The
AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the
industry-standard 80C51 instruction set and pin out. The on-chip Flash allows
the program memory to be reprogrammed in-system or by a conventional
nonvolatile memory programmer. By combining a versatile 8-bit CPU with
in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a
powerful microcontroller which provides a highly-flexible and cost-effective
solution to many embedded control applications.
The
AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit
timer/counters, a six-vector two-level interrupt architecture, a full duplex
serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52
is designed with static logic for operation down to zero frequency and supports
two software selectable power saving modes. The Idle Mode stops the CPU while
allowing the RAM, timer/counters, serial port, and interrupt system to continue
functioning. The Power-down mode saves the RAM con-tents but freezes the
oscillator, disabling all other chip functions until the next interrupt or
hardware reset
Pin
Description
VCC: Supply voltage.
GND: Ground
Port 0
Port 0 is
an 8-bit open drain bidirectional I/O port. As an output port, each pin can
sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used
as high-impedance inputs. Port 0 can also be configured to be the multiplexed
low-order address/data bus during accesses to external program and data memory.
In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes
during Flash programming and outputs the code bytes during program
verification. External
pull-ups are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional
I/O port with internal pull-ups. The Port 1 output buffers can sink/source four
TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL) because of the internal
pull-ups.
In
addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external
count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively,
as shown in the following table. Port 1 also receives the low-order address
bytes during Flash programming and verification.
Port 2
Port 2 is
an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are
pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
2 pins that are externally being pulled low will source current (IIL) because
of the internal pull-ups. Port 2 emits the high-order address byte during
fetches from external program memory and during accesses to external data
memory that uses 16-bit addresses (MOVX @ DPTR).
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The
Port 3 output buffers can sink/source four TTL inputs. When 1s are written to
Port 3 pins, they are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally being pulled low will source
current (IIL) because of the pull-ups. Port 3 receives some control signals for
Flash programming and verification. Port 3 also serves the functions of various
special features of the AT89S52, as shown in the following table.
RST: Reset input. A high on this pin for two machine cycles while the
oscillator is running resets the device. This pin drives high for 98 oscillator
periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH)
can be used to disable this feature. In the default state of bit DISRTO, the
RESET HIGH out feature is enabled.
Address
Latch Enable (ALE) is an output pulse for latching the low byte of the address
during accesses to external memory. This pin is also the program pulse input (PROG
In normal
operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency
and may be used for external timing or clocking purposes. Note, however, that
one ALE pulse is skipped during each access to external data memory.
If
desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH.
With the bit set, ALE is active only during a MOVX or MOVC instruction.
Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
PSEN
Program
Store Enable (PSEN) is the read strobe to external program memory.
When the AT89S52 is executing code from external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations
are skipped during each access to external data memory.
EA/VPP
External
Access Enable.
EA Must be
strapped to GND in order to enable the device to fetch code from external
program memory locations starting at 0000H up to FFFFH. Note, however, that if
lock bit 1 is programmed,
will be
internally latched on reset.
External
Access Enable.
Must be
strapped to GND in order to enable the device to fetch code from external
program memory locations starting at 0000H up to FFFFH. Note, however, that if
lock bit 1 is programmed,
EA will be
internally latched on reset.
EA: Should be strapped to VCC
for internal program executions.
This pin
also receives the 12-volt programming enable voltage (VPP) during Flash
programming.
XTAL1
Input to
the inverting oscillator amplifier and input to the internal clock operating
circuit.
XTAL2
Amplifier
Output from the inverting oscillator.
Note: C1, C2= 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for
Ceramic Resonators.